Field of the Invention
The present invention generally relates to non-volatile semiconductor memory devices, and more particularly to a non-volatile semiconductor memory device using a programmable and erasable floating-gate type memory cell. More specifically, the present invention is concerned with a non-volatile semiconductor memory device using floating-gate type memory cells as redundant information memory elements.
There is a demand to reduce the operation voltage in order to suppress power consumed in various semiconductor devices as portable devices are widely used in practice. Particularly, non-volatile semiconductor memory devices such as flash memories are equipped with programmable and erasable memory cells of the floating-gate type are required to reduce the threshold voltage of the memory cells to of a power supply voltage approximately equal to 1.5V.
A description will now be given, with reference to FIG. 1, of a conventional non-volatile semiconductor memory device.
FIG. 1 shows a structure of a peripheral circuit of a floating-gate type memory cell used in a conventional non-volatile semiconductor memory device. The peripheral circuit includes a floating-gate type memory cell 101, p-channel transistors 102 and 104, and an inverter 103. The memory cell 101 has a polysilicon gate embedded in a gate oxide film. The memory cell 101 can be programmed by applying a high voltage equal to, for example, 12 V or 21 V. Thus, electrons are injected into the polysilicon gate of the cell 101. The electrons can be drawn from the polysilicon gate by applying another high voltage, so that data stored in the memory cell can be erased. The threshold voltage of the memory cell is varied in accordance with the voltage applied to the polysilicon gate thereof.
A description will be given of a programming operation, an erase operation and a data read operation of the conventional non-volatile semiconductor memory device, assuming that the threshold voltage of the memory cell transistor is approximately equal to 2 V when there are no electrons in the gate (the initial state) and is approximately equal to 5 V when there are electrons in the gate.
In the programming operation, the threshold voltage of the memory cell cell 101 can be increased to 5 V or higher as follows. A control gate voltage Vcg as high as approximately 10 V is applied to the control gate of the memory cell cell 101. A drain voltage Vd which is as high as approximately 5 V and results from a programming voltage Vpgm is applied to the drain (Nb) of the memory cell cell 101. A source voltage Vs of 0 V is applied to the source of the memory cell cell 101. Hence, electrons are injected into the floating ate of the memory cell cell 101. The electrons thus injected are maintained even in the power-off state because floating gate is totally enclosed by an insulating substance.
In the erase operation, the threshold voltage of the memory cell cell 101 is set to approximately 2 V as follows. The control gate voltage Vcg as high as approximately -10 V is applied to the control gate of the cell cell 101. The drain of the cell cell 101 is set to the open state. The source voltage Vs of approximately 5 V is applied to the source of the cell cell 101. Thus, the electrons in the floating gate are drawn. The state in which the electrons have been drawn can be maintained even in the power off state because the floating gate is totally enclosed by the insulating substance.
The data read operation is carried out as follows. When a data read operation on the cell cell 101 takes place in the state in which the electrons have been drawn, a read select signal /RD.sub.-- sel ("/" corresponds to "bar" attached above the symbol in FIG. 1 and denotes "active low") is set to a low level. Thus, the p-channel transistor 102 is turned ON. Simultaneously, the control gate voltage Vcg approximately equal to 3 V is applied to the control gate of the cell cell 101. At that time, the cell cell 101 has a threshold voltage of approximately equal to 2 V, and is thus ON. Thus, a current is pulled to the ground GND, and the node Nb is changed to the low level. As a result, a high-level signal is output to an output terminal OUT via an inverter 103.
When the data read operation takes place in the state in which the electrons have been injected, the read select signal /RD.sub.-- sel is set to the low level. Simultaneously, the control gate voltage Vcg approximately equal to 3 V is applied to the control gate of the cell cell 101. At that time, the cell cell 101 is turned OFF because the cell cell 101 has a threshold voltage of approximately 5 V. The node Nb is switched to the high level. Thus, a low-level signal is output to the output terminal OUT via the inverter 103.
The conventional non-volatile semiconductor memory device having the above memory cell 101 has, in addition to the above-mentioned operations, the function of storing initial information concerning the device using the floating-gate type memory cell 101, that is, the non-volatile property. For example, the floating-gate type memory cell 101 can be utilized as a redundant memory cell used when a fault occurs. An access to a faulty cell is automatically switched to a redundant memory cell by referring to the information stored in the redundant information memory element.
When the memory cell 101 is utilized as the redundant information memory element, data is read from the conventional non-volatile semiconductor memory device by any of the following first through third methods. The first method is to read data while the control gate voltage Vcg equal to 3 V is always applied. The second method is to read data only when the control gate voltage Vcg equal to 3 V is applied as necessary. The third method is to read data by storing fixed information generated by a fuse element or the like which is an element having the function of physically breaking a connection such as a switch.
The conventional non-volatile semiconductor memory device is required to operate at a reduced voltage in order to suppress power consumption. Thus, there is a possibility that the power supply voltage Vcc may become lower than the control gate voltage Vcg. When such a situation occurs, the following problems are encountered.
When the first method is employed, the non-volatile semiconductor memory device needs a boost circuit which always boosts the power supply voltage Vcc to 3 V. Thus, the first method needs an increased chip area and consumes a large amount of power. Further, it takes a long time to completely boost the power supply voltage Vcc to 3 V after power on, so that data cannot be read soon.
When the second method is employed, the non-volatile semiconductor memory device needs a boost circuit which always boosts the power supply voltage Vcc to 3 V, and thus needs an increased chip area. Further, it takes a long time to completely boost the power supply voltage Vcc to 3 V from receipt of a data read command, that is, the time when the read select signal /RD.sub.-- sel switches to the low level. Thus, data cannot be read soon. Furthermore, it takes another long time to completely boost the power supply voltage Vcc to 3 V after power on, so that data cannot be read soon.
When the third method is employed, a particular apparatus is needed to cut the fuse element by projecting a laser beam onto the fuse. Further, programming of data is no longer available once the fuse is cut.